The present invention relates to an output driver circuit which is used to output data in all sorts of semiconductor memory devices, and more particularly, to a semiconductor memory device and a method for operating the same, which can improve system integrity (SI) by adjusting the slew rate of the output driver circuit appropriately according to system conditions.
The slew rate acts as a barometer indicating the change of output voltage per unit time.
FIG. 1 illustrates the definition of slew rate in the Joint Electron Device Engineering Council (JEDEC) specification.
VOH(AC) represents a high level alternating current (AC) output, and VOL(AC) represents a low level AC output.
The transition time of a rising edge is defined by a time DeltaTRse from VOL(AC) to VOH(AC), and the transition time of a falling edge is defined by a time DeltaTFse from VOH(AC) to VOL(AC).
The slew rate of the rising edge is defined by “(VOH(AC)−VOL(AC))/DeltaTRse”, and the slew rate of the falling edge is defined by “(VOH(AC)−VOL(AC))/DeltaTFse”.
FIG. 2 is a structure diagram illustrating connection configuration between a memory controller and a dual in-line memory module (DIMM).
Referring to FIG. 2, input/output (I/O) data and address (ADD)/command (CMD) between the DIMMs 2000 . . . 200n and the memory controller 210 are shared between the DIMMs in a serial stub scheme. The output CLK of clock driver 220 is supplied to the DIMMs 2000 . . . 200n and the memory controller 210. Each DIMM 2000 . . . 200n has multiple DRAMS, e.g. DRAM0 . . . DRAMn can be seen on DIMM 200n.
FIG. 3 illustrates setting the mode register set (MRS) of the termination resistance (RTT) of a double data rate 3 (DDR3) memory device designated in the JEDEC specification.
RTT is the termination resistance of an output driver circuit.
As is well known, the output driver circuit terminates an output node (i.e., data pin) to a pull-up level and outputs logic high data. Furthermore, the output driver circuit terminates the output node to a pull-down level and outputs logic low data. The termination resistance denotes a resistance when the output driver circuit terminates the output node for outputting data.
The setting of RTT is adjusted using addresses A9, A6 and A2, and thus RTT may be adjusted to RZQ/4, RZQ/2, RZQ/6, RZQ/12, RZQ/8, etc. Herein, RZQ denotes a resistance of an external resistor connected to the ZQ node of a memory device, and RZQ becomes generally 240Ω. Accordingly, according to the present regulations of the DDR3, RTT may be set to 60Ω, 120Ω, 40Ω, 20Ω, 30Ω, etc.
The reason why RTT is variously adjustable is that configurations of single loading/double loading are possible according to configuration such as how many DIMMs are inserted in a memory slot and a suitable RTT is selected according to system conditions.
FIG. 4 is a circuit diagram of an output driver circuit of the conventional semiconductor memory device.
Referring to FIG. 4, the conventional output driver circuit includes a pre-driver 410, a pull-up driver 420, and a pull-down driver 430.
The pre-driver 410 generates a pull-up control signal UP_PRE and a pull-down control signal DN_PRE according to a logical value of data to be output.
In operation, an enable signal EN is used to determine a state of an output node DQ. When the enable signal EN is deactivated to ‘LOW’, the pull-up control signal UP-PRE is deactivated to ‘HIGH’ and the pull-down control signal DN_PRE is also deactivated to ‘LOW’. Thus, the output node DQ maintains a high impedance (Hi-Z) state (no output data).
When the enable signal EN is activated to ‘HIGH’, data may be output. When data to be output is logic high data, a DATAR signal becomes ‘HIGH’. Accordingly, the pull-up control signal UP-PRE is activated to ‘LOW’ so that the pull-up driver 420 is turned on. Therefore, logic high data are output through the output node DQ. On the other hand, when data to output is logic low data, a DATAF signal becomes ‘HIGH’. Thus, the pull-down control signal DN_PRE is activated to ‘HIGH’ so that the pull-down driver 430 is turned on. Consequently, logic low data are output through the output node DQ.
A plurality of inverters 411 and 412, which are connected in parallel and disposed in respective output terminals outputting the pull-up control signal UP-PRE and the pull-down control signal DN_PRE, are included for adjusting the slew rate. As the number of signals activated to ‘HIGH’ among signals T<#> increases, the number of inverters enabled among the parallel inverters 411 and 412 increases so that the slew rate increases.
Controller 413 of FIG. 4 adjusts the number of signals activated to ‘HIGH’ among the signals T<#> (inverted as TB<#>) according to a test mode signal TEST_MODE, and thus adjusts the slew rate in accordance with a test mode.
The pull-up driver 420 is turned on to terminate the output node DQ to a pull-up level when the pull-up control signal UP-PRE is activated to ‘LOW’. Accordingly, the output node DQ is changed to ‘HIGH’ so that logic high data are output. The pull-up driver 420 includes a single PMOS transistor in FIG. 4, but the pull-up driver 420 may include a plurality of PMOS transistors connected in parallel. How much resistance the pull-up driver 420 has, that is, how many transistors are used among parallel-connected transistors, is determined by the setting of RTT of FIG. 3. In more detail, a target resistance of the pull-up driver 420 is determined by the setting of RTT of the FIG. 3, which experiences a fine calibration process for maintaining a constant resistance in spite of changes of a process, a voltage and a temperature (PVT). These contents are well known to those skilled in the art, and thus further detailed description will be omitted.
The pull-down driver 430 is turned on to terminate the output node DQ to a pull-down when the pull-down control signal DN_PRE is activated to ‘HIGH’. Accordingly, the output node DQ is changed to the ‘LOW’ state so that logic low data are output. The pull-down driver 430 also includes a single NMOS transistor in FIG. 4, but the pull-down driver 430 may include a plurality of NMOS transistors connected in parallel. In more detail, a target resistance of the pull-down driver 430 is determined by the setting of RTT of the FIG. 3, which experiences a fine calibration process for maintaining a constant resistance in spite of the changes of PVT.
That is, the conventional output driver circuit includes a configuration for changing the slew rate, but such a slew rate is changed for the purpose of a test in testing.
As described above, the JEDEC specification defines regulations for adjusting RTT appropriately according to system conditions.
When the RTT of the conventional output driver circuit is changed, it is apparent that the signal integrity (SI) is also changed by the change of loading in the output node DQ. However, since the conventional output driver circuit does not at all take into consideration of the change of the slew rate according to the change of RTT in spite of the change of RTT, an error may occur in the signal integrity (SI).